Fault Injection for Verifying Testability at the VHDL Level
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چکیده
This paper presents a technique to improve verification at the VHDL level of digital circuits by means of a specially designed fault injection block. The injection technique allows incorporation of both transient and permanent faults to varying levels of VHDL hierarchy, and helps in verifying the performance of a testable system.
منابع مشابه
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تاریخ انتشار 2003